During the manufacture of semiconductor technology, films of various materials are sequentially deposited and patterned on a semiconductor substrate such as a silicon substrate. For the back-end-of-line (BEOL) processing, these materials include metallization levels for the interconnect structures, dielectric levels used for insulation and capping, and barrier layers to prevent diffusion and oxidation of the interconnects. The current choice for interconnect metallization is copper, manufactured in a dual-damascene method. Dielectric materials include silicon oxide, deposited by the plasma enhanced chemical vapor deposition (PECVD) using silane (SiH4) or tetraethylorthosilicate (TEOS) precursors, or organosilicate glass or borophosphosilicate glass (BPSG), deposited by chemical vapor deposition (CVD) for high-performance interconnect applications. The organosilicate glass can be in its dense form or in a form that includes porosity.
The choice of barrier layers includes tantalum, tantalum nitride, tungsten nitride, ruthenium and titanium and alloys of these metals.
The current deposition method for the copper metallization process involves electroplating of the copper either onto a conductive seed layer or directly onto the barrier layer materials. An applied current or voltage is placed on the patterned wafer in the presence of an electrochemical plating bath containing copper ions. As the aspect ratios of semiconductor metallization features increases, the ability to completely fill these features by electroplating becomes more difficult. Voids or seams can occur in semiconductor metallization trenches, leading to interconnect structures with higher resistivity and often higher susceptibility to reliability failures (such as electromigration).
FIG. 1 depicts the edge of a typical semiconductor array of fine line features in cross-section. These features consist of copper (101) electroplated either onto a conductive seed layer or directly onto the barrier layer material (102). The lines are separated by dielectric material (103), such as silicon oxide deposited by PECVD or organosilicate glass deposited by CVD. Although the plating characteristics have been optimized for plating across the entire wafer, local non-uniformities in the electrochemical potential at the edges of such arrays can cause voids (104) or seams to form in the features.
By altering the chemical composition in the plating bath, through additives that provide differential kinetics of copper plating at the flat wafer surface and in the inlaid features, one can optimize the deposition to minimize the occurrence of voiding. In addition, one can reduce the occurrence of voids and seams by tailoring the current which is applied to the wafer during plating. Along these lines see Andricacos et al., US patent application publication 2004/0069648 A1. Although these techniques can be used to minimize the onset of voids over the entire wafer, the local uniformity of the fill of semiconductor features may vary so that edges of interconnect arrays can be more susceptible to voiding issues. This is due to the lower fraction of metal present at the edge of such arrays, which alters the current distribution relative to that at the center of the arrays. Because the copper progression front works from the wafer edge (in contact with one of the electrodes) towards the wafer center, voiding issues are more likely to be observed at the side of any metallization array which is closest the wafer edge, and less so at the side of the array closest to the wafer center.
A method that can provide more uniform reduction in voiding or seams across entire microcircuitry arrays on a chip without significantly altering the plating conditions (chemistry and plating current) which are optimized for plating across the wafer would be desirable.